1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to a method for manipulating and repartitioning a hierarchical design.
2. Description of the Related Art
Integrated circuit design flow is a complex process. Most often, a functional/behavioral description of the system/circuit is created with use of a register transfer language (RTL) or hardware description language (HDL) such as Verilog or VHDL (Very high speed integrated circuits Hardware Description Language). An important part of the design process is the creation of a logic implementation, and subsequently a transistor level implementation of these behavioral models. The creation of these implementations is oftentimes automated through the use of “synthesis” tools. Generally, a synthesis program is used to generate a netlist from the HDL models, making use of standard cell libraries containing a variety of circuit elements from which the integrated circuit may be constructed. Netlists usually include instances of the standard cells contained in the design, with the possible inclusion of custom blocks, and information descriptive of the connectivity between all the instances included in the integrated circuit. There are different types of netlists that can be used, including physical and logical netlists, instance-based and net-based netlists, and flat and hierarchical netlists. Typically, the final netlist generated by the synthesis tool is dependent on the constructs that appear in the HDL model. In other words, the style and syntax of various functional elements in the HDL oftentimes determines the type of elements and components that appear in the netlist generated by the synthesis tool.
In digital designs there is typically a primary input that will reset the design, placing the state of the machine in a suitable starting point for it to begin to operate. The basic component, or gate/element that is used to hold a particular state (i.e. either a high state—‘1’, or a low state—‘0’) is typically referred to as a flop (or flip-flop, oftentimes abbreviated as ‘FF’), or more generally referred to as a latch. As mentioned above, most digital designs are typically coded in RTL to specify the design on a functional/logical level. In other words, RTL provides a high level, abstract, view of the design. As also mentioned above, the synthesis tool is used to convert the abstract RTL into a gate level netlist, leaving the design represented in constructs that directly map to constructs available in silicon. Because routing the reset signal—that is, the signal intended to reset the flops—around the design takes area, and because resettable-flops are typically larger than non-resettable-flops, most designs strive to include only the minimal number of resettable-flops. To put it another way, due to the size increase when a flop is made resettable, the goal in most designs is to minimize the number of flops that have to be resettable.